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PCI Bus Performance
The PCI is the highest performance general I/O bus currently used on PCs. This superior performance of the PCI bus is due to several factors:

• Burst mode: The PCI bus can transfer information in a burst mode, where after an initial address is provided multiple sets of data can be transmitted in a row. This works in a manner similar to how cache bursting works
• Bus Mastering: PCI supports full bus mastering, which leads to improved performance.
• High Bandwidth Options: The PCI 2.1 version is expanded to 64 bits and 66 MHz, thus quadrupling the bandwidth.

PCI Internal Interrupts
The PCI bus uses its own interrupt system for dealing with requests from the cards on the bus. These interrupts are often called "#A", "#B", "#C", "#D" to avoid confusion with the normal sytem IRQs (they are sometimes called "#1" to "#4" as well). These interrupts if needed by cards in the alots are mapped to regular interrupts, normally IRQ9 through IRQ12. The PCI slots in most systems can be mapped to at most 4 regular IRQs. In systems having more than 4 PCI slots two or more PCI devices share an IRQ.

PCI Bus Mastering
Bus mastering is the ability of devices on the PCI bus (other than the system chipset) to take control of the bus and perform transfers directly. The PCI bus is the first bus to popularize bus mastering. PCI's design allows bus mastering of multiple devices on the bus simultaneously, with the arbitration circuitry working to ensure that no device on the bus (including the processor) locks out any other device. At the same time it allows any given device to use the full bus thoroughput if no other device needs to transfer anything. Thus it acts as a tiny local network within the computer in which multiple devices can talk to each other through a communication channel managed by the chipset.
The PCI bus also allows you to setup compatible IDE/ATA hard disk drives to be bus masters. This can increase the performance over the use of PIO modes, which are the default way of data transfering used by IDE/ATA. However for IDE bus mastering to work properly and correctly all of the following are needed:

• Bus Mastering Capable system hardware: This includes the motherboard, chipset, bus and BIOS. Most of the newer motherboards using Intel 430 PEntium chipset family will support bus mastering IDE.
• Bus Mastering hard disk: All Ultra ATA hard disks support bus mastering
• 32 bit Multitasking OS
• Bus Mastering drivers: A special driver must be provided to the OS to enable bus mastering to work.

The PCI protocol
The PCI bus uses an intermediate protocol rather than a register to register protocol. With a conventional PCI device, the following steps occur when the device switches a control signal:

1. On the rising clock edge, the device switches the signal to a high or low state onto the PCI bus.
2. The signal propagates across the bus (propagation delay).
3. during the same clock cycle, the receiving device decodes the signal to determine whether the signal is for the receiving device and to determine if ir must respond by switching one of its outputs.
4. The receiving device responds immediately, that is in the next clock cycle.

With a 33MHz clock frequency the time allocated to the decode logic is of the order of 7 nanoseconds of the total 30ns clock cycle time. At 33MHz this is sufficient time for the receiving device to respond on the next rising clock edge. However an important bottleneck or problem with this protocol is that when the clock frequency is doubled to 66MHz (thus reducing the clock cycle time to 15ns), the number of nanoseconds available for the receiving device to respond is cut down to 3ns. Thus there is a severe time constraint for the conventional PCI bus which makes it difficult for the PCI bus to adapt to 66MHz. Dating from the mid 1995s, the main performance critical components of the PC communicated with each other across the PCI bus. Most common of these PCI devices were the disk and graphics controllers which were either mounted onto the motherboard or on expansion cards in PCI slots. Moreover by the late 1990s new processors and I/O devices were demanding much higher I/O bandwidth than PCI could deliver. This resulted in creation of higher bandwidth buses like the PCI-X bus.

2.2.4 PCI-X Bus

The PCI-X is a high performance addendum to the PCI local bus specification developed in collaboration by IBM, HP and Compaq. The PCI-X is generally viewed as an immediate solution to the increased I/O requirements for high bandwidth enterprise applications such as Gigabit ethernet, fibre channel and high performance graphics. The PCI-X technology increases bus capacity to more than eight times that of the conventional PCI bus bandwidth, from 133 Mbps with the 32 bit 33 MHz PCI bus to 1066Mbps with the 64 bit 133MHz PCI-X bus. It also enhances the PCI protocol to develop an interconnect that exceeds raw bandwidth of 1 Gbps. The following sections briefly describe some of the key elements of the PCI-X technology:

Register to Register protocol
With the PCI-X register-to register protocol the following steps occur:

1. On the rising clock edge, the device switches the signal to a high or low state onto the PCI-C bus.
2. The signal propagates across the bus.
3. The signal is sent to a register or flip-flop, that holds the signal until the nexy clock cycle.
4. The receiving device has a full clock cycle to decode the signal and determine the proper response.
5. The receiving device responds two full clock cycles after the sending device first switched the signal.

Thus the PCI-X considerably eases the time constraints that were a bottleneck for the PCI bus by providing an entire clock cycle for the decoding logic to occur. The net difference is that the PCI-X transactions will require an additional clock cycle more than the conventional PCI transaction. With the timing constraint reduced it is much easier to design and implement adapters and systems to operate at 66MHz and greater.