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2.1.4 AMD x86 Compatible Processors
The AMD x86-64 or AMD64 is a 64 bit pricessor architecture invented by AMD. Its is a superset of the x86 architecture (discussed in 2.1.2) which it natively supports. The AMD64 instruction set is currently being used in AMD's Athlon 64, Athlon 64 FX and Opteron processors. An important part of AMD64 is tht it allows the latest in processor innovation to be brought to the existing installed base of 32 bit applications and operating systems, while establishing an installed base of systems that are 64 bit capable. For example the IA-64 offers no native x86 compatibility, meaning that existing 32 bit applications are not anticipated ti run with leading edge performance on IA-64 technology based processors. Instaed the AMD64 provides extensions to the reliable, proven and high performance x86 instruction set and preserver full compatibility between 32 and 64 bit environments.
AMD64 Architecture Overview
The AMD64 architecture extends the x86 architecture by introducing two major features: a 64 bit extension called long mode and register extensions. The new modes are encoded using two flags in the segment decsriptor. The first flag in the existing "D" bit that controls the size of operands, a second bit is a previously unused "L" bit which is used for determining if specific applications are 64 bit enabled or are run in compatibility mode.
Long mode
Long mode is enabled by a global control bit called LMA (Long mode Active). When LMA is disabled, the processor operates as a standard x86 processor and is compatible with all existing 16 and 32 bit operating systems and applications. When LMA is activated (LMA = 1), the 64 bit processor extensions are enables. Thus the system can auto configure according to the capabilities of the machine and the processor. Long mode consists of two sub modes:- 64 bit mode: This mode supports the following new features:
- 64 bit virtual addresses (implementations can have less)
- Register extensions through a new prefix (REX) which adds eight GPR (R8-R15), widens GPRs to 64 bits and adds eight 128 bit Streaming SIMD extension (SSE) registers (XMM8-XMM15)
- 64 bit instruction pointer (RIP)
- new RIP data addressing mode
- Flat address space with single code, data and stack space. Since the 64 bit mode supports a 64 bit virtual address space, it requires a 64 bit operating system and tool chain. A few instruction opcodes and prefix bytes are redefined to allow the register extensions and 64 bit addressing.
The default address size is 64 bits and the default operand size is 32 bits. The defaults can be overriden on an instruction-by-instruction basis using prefixes. A new REX prefix is introduced for specifying 64 bit operand size and the new registers. This mode is enabled by the OS on an individual code segment basis. The new register extensions added via the new REX prefix add eight 64 bit GPRs (R8-R15), eight 128 bit streamimg SIMD Extensions registers (XMM8-XMM15) and widens all GPRs and the instruction pointer to 64 bits. The instruction pointer is also widened to 64 bits. - Compatibility mode: Compatibility mode supports binary compatibility with existing 16 and 32 bit applications within a 64 bit environment.In compatibility mode the applications can only access the first 4 GB of virtual address space. As with the 64 bit mode, compatibility mode is enabled by the OS on an individual code segment basis. However unlike the 64 bit mode, x86 segmentation functions normally using either the 16 bit or 32 bit protected mode semantics. From the application's point of view the compatibility mode looks like a legacy x86 protected mode environment. From the OS's point of view, address translation, interrupt and exception handling and system data structures use the 64 bit long mode mechanisms.
Register Extensions
To define the addressing logic for the registers, the AMD64 architecture simply extends the addressing scheme currently used for 16 and 32 bit instructions. For example for 16 bit operations, the two bytes of register A are addressed as AX, for 32 bit operations four bytes of register A are addressed as EAX and for 64 bit operations the eight bytes are addresses as RAX.
In 64 bit mode the general purpose registers (GPRs) are extended to 64 bits. The 64 bit registers are called RAX,RBX,RCX,RDX,RDI,RSI,RBP,RSP,RIP and RFLAGS. The new 64 bit registers overlay and extend the existing registers. Besides 8 new 64 bit GPRs are added for a total of 16 GPRs. There are also eight new streaming SIMD registers for a total of 16 SIMD registers. These new SIMD registers are called XMM8 through XMM15. Segment registers (ES, DS, FS, GS and SS) are ignored in the 64 bit mode. Code segments still exist however. The CS is needed to encapsulate the defult mode of the processor as well as the execution privilege level. When performing 32 bit operations the destination register being a GPR, the 32 bit value will be zero extended into the full 64 bit GPR. 8 bit and 16 bit operations on GPRs preserve all unwritten upper bits. This preserves the 16 and 32 bit semantics for partial width results. The final step is to simply define a set of instructions prefixes that specify a 64 bit operand size and allow access to the new registers. This is similar to the the method used to extend the x86 architecture for other funtionalities such as AMD's 3DNOW! technology.
Thus by extending the x86 core rather than replacing it with a new, entirely different instruction set, AMD64 makes the transition to 64 bit much easier, faster and less expensive. The problem of migrating to a new architecture is greatly reduced, without limitung the forward compatibility and future performance of existing applications.
