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Floating point stack registers
There are 8x87 floating point registers known as ST(0) to ST(7). these registers are accessible like a FIFO stack. The register numbers are not fixed but are relative to the top of the stack; ST(0) being the top of the stack, ST(1) is the next one below the top and so on. That means that data is always pushed down from the top of the stack and operations are always done against the top of the stack. As a result these registers can only be accessed in the stack order and not randomly.
SIMD registers
These include the MMX, 3DNow! and SSE registers.
MMX registers
MMX added 8 registers to the architecture known as MM0 through to MM7. These registers are just aliases for existing x87 FPU stack registers. Hence anything that is done to the floating point stack would also affect the MMX registers. Unlike the FP stack, the MMn registers are fixed and not relative so that they are randomly accessible. Each of these registers are 64 bit integers. However one of the main concepts of the MMX instruction set is that of packed data types, which means that instead of using the whole register for a single 64 bit integer two 32 bits or four 16 bits or eight 8 bits integers may be used.
3DNow! registers
3DNow! was designed to be a natural evolution of MMX from integer to floating point. It uses the same name convention as MMX registers (MM0 to MM7), the only difference being that one could pack single precision floating points into these registers. Due to the aliasing with the FPU registers, same instruction and data structures which are used to save the state of the FPU registers can be used for these registers.SSE registers
SSE is a SIMD instruction set that works only on floating point values, like 3DNow!. However unlike 3DNow! it has no connection with the FPU stack. It has larger registers than 3DNow! and can pack twice the number of single precision floats. The original SSE was designed for handling single precision only, but then the SSE2 was introduced for double precision numbers, which the 3DNow! could not handle as a double precision number is 64 bit in size which would be the full size of a single 3DNow! MMn register. At 128 bit the SSE2 can pack two double precision floats into one register. Thus SSE2 is much more suitable for scientific calculations than either SSE1 or 3DNow!.Memory management
The memory that the processor addresses on its bus is called the physical memory. Physical memory is organized as a sequence of 8-bit bytes. Each byte has an unique address called physical address which ranges frm 0 to 64 Gb. Any operating system designed to work with the IA-32 will use its processor memory management facilities which provides features like segmentation, paging etc. With the flat memory model, memory appears to a program as a single continous address space called linear address space. This is byte addressable. With the segmented memory model, memory appears to a program as a group of independent address spaces called segments. When using this model, code , data and stacks are typically contained in separate segments. To address a byte in a segment, a program muct issue a logical address or far pointer. The programs running on an IA-32 processor can address upto 16383 segments of different sizes and types. The primary reason for using a segmented memory is to increase the reliability of programs and systems. For example placing a program's stack in a separate segment prevents the stack from growing into the code or data space and overwriting instructions or data. With either the flat or segmented memory model, the linear address space is mapped into the processor's physical address space either directly or through paging. When using direct mapping, each linear address has a one-to-one correspondence with a physical address. On the other hand when using the IA-32's paging mechanism, the linear address space is divided into pages which are mapped into virtual memory. The pages of virtual memory are then mapped as needed into physical memory.
The real address mode memory model uses the memory model for the Intel 8086 processor. This memory model is supported in the IA-32 architecture for compatibility with existing programs written to run on 8086 processors. The real address mode uses a specific implementation of segmented memory in which the linear address space for the program and the operating system/executive consists of an array of segments of upto 64 KB in size each.
