General Cluster Nodes

 

Overview

This chapter contains an expansion of the definitions presented in the first chapter, and lays groundwork for the following sections.

 

2.1 Processor and Memory Choices

This section contains an overview of the different processors that are available for use in a beowulf cluster. This section contains a brief overview of x86 compatible and other than x86 CPUs. A more in depth analysis of IA-32 CPUs by Intel and AMD and IA-64 are also presented. Low level processor, and memory subsystem performance are discussed briefly. An overview of memory architecture is also presented.

2.1.1 Common Processor Architectures

 

2.1.2 Intel 32 bit Processors

The IA-32 is sometimes generically called x86 or even x86-32. The term means Intel Architecture, 32 bit which distinguishes it from the 16 bit versions that preceded it and the 64 bit version referred to as IA-64 that followed it. Within various programming language directives it is also referred to as i386; this directive would inform the compiler to generate code only for the IA-32 instruction set. This instruction set was introduced in the Intel 80386 microprocessor in 1985. Even though the basic instruction set has remained intact the successive generation of microprocessors that run it have become much faster at running it. The biggest supplier and inventor of this class of processors is Intel. However it is not the only supplier of this family of processors. The second biggest supplier is AMD and there are also numerous even smaller specialized supplier of these processors. The following sections will briefly describe the various features of the IA-32 family of processors.

Modes of operations

The IA-32 supports three basic operating modes refered to as the Real Mode, the Protected Mode and the Syetm Management mode. The operating mode determines which instructions and architectural features are accessible to the processor. For example in the Real Mode the processor is limited to accessing just 1Mb of memory, while in the Protected Mode it can access all its memory.

Real Mode

Once the machine is booted the processor initiates itself into the Real Mode and then starts loading programs automatically into RAM from ROM and disk.A program inserted somewhere along the boot sequence maybe used to put the processor into the Protected Mode.

Protected mode

This mode is the native state of the processor. In this mode all instructions and architectural features are available providing the highest performance and capability. Besides having the additional memory addressability ability various other advantageous features get activated as well. One of them is the protected memory which prevents programs from corrupting each other. another one is the virtual memory, which lets programs use more memory than is physically installed on the machine. And the third feature is task switching known as multitasking, which lets a computer juggle multiple programs all at once to look like they are running at the same time. Another important feature of the Protected mode is the ability to directly execute "real address mode" 8086 software in a protected, multitasking environment. This feature is called te virtual-8086 mode, though strictly speaking it is not an actual processor mode. It is infact a protected mode attribute that can be enabled for any task.

The size of the memory in Protected mode is limited to 4Gb. But this isnt the limit of the memory size in IA-32 processors. Using tricks in the processors' page and segment memory management systems (for example Physical address extension or PAE), IA-32 maybe able to access much more than the 32 bits address space, even without switchover to the 64 bit family of processors.

System Management mode (SMM)

This mode provides an operating system or executive with a transparent mechanism for implementing platform specific fucntions such as power management and system security. The processor enters SMM when the external SMM interrupt pin (SMI#) is activated or an SMI is received from the advanced programmable interrupt controller (APIC). In SMM, the processor switches to a separate address space while saving the basic context of the currently running program or task. SIMM-specific code may then be executed transparently. Upon returning from SMM, the processor is placed back into its state prior to the system management interrupt. SMM was introduced with the Intel386 SL and Intel486 SL processors and is a standard IA-32 feature.

Registers

The 386 has eight 32 bit general purpose registers for application use. There are 8 floating point stack registers. Other processors added new registers with various SIMD instruction sets such as MMX, 3DNow! and SSE. There are also system registers that are used mostly by operating systems but not by applications. These include segment, control, debug and test registers. There are 6 segment registers used mainly for memory management. The number of control, debug or test registers varies from model to model.

General Purpose Registers

8 bit and 16 bit register subsets

8 bit and 16 bit substes of these registers are also accessible. For example the lower 16 bits and 32 bit EAX registers can be accessed by calling it the AX register. Some of the 16 bit registers can be further subdivided into 8 bit subsets, for example, the upper 8 bit half of AX is called AH and the lower half is called AL. Similarly EBX is subdivided into BX (16 bit) and BH and BL (8 bit each).

General data registers

• EAX Accumulator (with a special interpretation for arithmetic instructions;a for accumulator).
• EBX base register (used for addressing data in the data segment)
• ECX counter (with a special interpretation for loops, c for counter)
• EDX data register

General Address registers

These are used for address pointing and include:

• EBP stack base pointer (holds base address of stack)
• ESI source index (for string operations)
• EDI destination index (for string operations)
• ESP stack pointer (holds top address of stack)
• EIP instruction pointer (holds current instruction address)
  
  
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